H5TQ1G63BFR-12C

Name: H5TQ1G63BFR-12C
Rating: 4.5 (10 reviews)

Lead-free, environmentally friendly construction

5,941 有效庫存

H5TQ1G63BFR-12C

有效庫存5,941

Lead-free, environmentally friendly construction

製造商零件號 # : H5TQ1G63BFR-12C
包裝/封裝: BGA-96
製造商: SKHYNIX
產品分類 : Controllers

品質保證

從我們的供應鍊網路採購的所有零件都經過嚴格的進貨檢驗流程。這種細緻的檢查可確保客戶收到的零件是正品並符合要求的標準。此外，我們還保存這些檢查的詳細記錄，以確保整個供應鏈的透明度和可追溯性。

認證

我們已成功獲得各項認證標準，並建立了自己的專業檢測實驗室。這確保了我們向客戶提供的每件產品都符合最高的品質標準。我們遵守嚴格的測試協議，以保持我們產品的一致性和準確性。為了確保我們的產品是原裝正品，我們還與信譽良好的第三方檢測機構合作進行嚴格的品質測試。我們對品質的承諾延伸到滿足行業、法律、監管和 ISO 9001:2015 的要求。

運輸與付款

關於運送

我們通常會在幾個工作日內通過可靠的運輸公司（例如 FedEx、SF、UPS 或 DHL）運送訂單。我們還支持其他運輸方式。如果您想詢問具體的運輸細節或費用，請隨時與我們聯繫。

關於付款

我們接受多種支付方式，包括VISA、MasterCard、銀聯、西聯、PayPal等渠道。

如果您有特定的付款方式或想詢問費率和其他詳細信息，請隨時與我們聯繫。

電匯

Paypal

信用卡

西聯匯款

速匯金

服務與包裝

About After Sales Service

All Parts Extended Quality Guarantee

自發貨之日起 90 天內發起申請。

與我們的工作人員確認退貨或換貨。

保持貨物收到時的原始狀態。

最後請注意，退貨或換貨的資格取決於對退貨商品實際狀況的評估。在完成退貨或換貨流程之前，我們將評估收到的貨物。如果您對退貨或換貨有任何疑問或需要進一步幫助，請隨時通過以下方式聯絡我們： [email protected]

關於包裝

在包裝方面，我們的產品均精心包裝在防靜電袋中，以提供ESD防靜電保護。外包裝堅固耐用且閉合牢固。我們支持各種包裝方法，例如捲帶式、切帶式、管式或託盤式。

例子

捲帶式

剪膠帶

管或託盤

H5TQ1G63BFR-12C 數據表

目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!

快速報價

請提交詢價 H5TQ1G63BFR-12C 或發送電子郵件給我們： Email: [email protected], 我們將在 12 小時內與您聯繫。

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公司名稱

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詳細說明

The H5TQ2G43CFR-xxC, H5TQ2G83CFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.FEATURES• VDD=VDDQ=1.5V +/- 0.075V• Fully differential clock inputs (CK, CK) operation• Differential Data Strobe (DQS, DQS)• On chip DLL align DQ, DQS and DQS transition with CK  transition• DM masks write data-in at the both rising and falling  edges of the data strobe• All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported• Programmable additive latency 0, CL-1, and CL-2  supported• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10• Programmable burst length 4/8 with both nibble  sequential and interleave mode• BL switch on the fly• 8banks• Average Refresh Cycle (Tcase of0 oC~ 95oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC• JEDEC standard 78ball FBGA(x4/x8)• Driver strength selected by EMRS• Dynamic On Die Termination supported• Asynchronous RESET pin supported• ZQ calibration supported• TDQS (Termination Data Strobe) supported (x8 only)• Write Levelization supported• 8 bit pre-fetch• This product in compliance with the RoHS directive.

主要特徵

VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK 
transition
DM masks write data-in at the both rising and falling 
edges of the data strobe
All addresses and control inputs except data, 
data strobes and data masks latched on the 
rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported
Programmable additive latency 0, CL-1, and CL-2 
supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
Programmable burst length 4/8 with both nibble 
sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of0 oC~ 95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
JEDEC standard 78ball FBGA(x4/x8)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
This product in compliance with the RoHS directive.

規格

以下是所選零件的基本參數，涉及零件的特性及其所屬類別。

Rohs Code	Yes	Part Life Cycle Code	Obsolete
Part Package Code	BGA	Pin Count !	96
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code !	8542.32.00.32	Access Mode !	MULTI BANK PAGE BURST
Access Time-Max	0.255 ns	Additional Feature !	AUTO/SELF REFRESH
Clock Frequency-Max (fCLK)	800 MHz	I/O Type	COMMON
Interleaved Burst Length	4,8	JESD-30 Code	R-PBGA-B96
Length	13 mm	Memory Density	1073741824 bit
Memory IC Type	DDR3 DRAM	Memory Width	16
Number of Functions	1	Number of Ports !	1
Number of Terminals	96	Number of Words	67108864 words
Number of Words Code	64000000	Operating Mode !	SYNCHRONOUS
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	64MX16	Output Characteristics	3-STATE
Package Body Material	PLASTIC/EPOXY	Package Code	TFBGA
Package Equivalence Code	BGA96,9X16,32	Package Shape	RECTANGULAR
Package Style	GRID ARRAY, THIN PROFILE, FINE PITCH	Power Supplies !	1.5 V
Qualification Status !	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	4,8	Standby Current-Max	0.025 A
Supply Current-Max	0.42 mA	Supply Voltage-Max (Vsup)	1.575 V
Supply Voltage-Min (Vsup)	1.425 V	Supply Voltage-Nom (Vsup)	1.5 V
Surface Mount !	YES	Technology	CMOS
Temperature Grade !	OTHER	Terminal Form !	BALL
Terminal Pitch !	0.8 mm	Terminal Position	BOTTOM
Width	7.5 mm