MT48LC8M16A2P-75
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54MT48LC8M16A2P-75
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
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服務與包裝
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MT48LC8M16A2P-75 數據表
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目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
General DescriptionThe 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits.Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.Features• PC100- and PC133-compliant• Fully synchronous; all signals registered on positive edge of system clock• Internal, pipelined operation; column address can be changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths (BL): 1, 2, 4, 8, or full page• Auto precharge, includes concurrent auto precharge and auto refresh modes• Auto refresh mode; standard and low power – 64ms, 4096-cycle (industrial) – 16ms, 4096-cycle refresh (automotive)• LVTTL-compatible inputs and outputs• Single 3.3V ±0.3V power supply• AEC-Q100• PPAP submission• 8D response time
主要特徵
- PC100- and PC133-compliant
- Fully synchronous; all signals registered on positive edge of system clock
- Internal, pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths (BL): 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- Auto refresh mode; standard and low power
- – 64ms, 4096-cycle (industrial)
- – 16ms, 4096-cycle refresh (automotive)
- LVTTL-compatible inputs and outputs
- Single 3.3V ±0.3V power supply
- AEC-Q100
- PPAP submission
- 8D response time
![MICRON Inventory MICRON Inventory](/files/uploads/inventory/micron/micron.jpg)
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Pbfree Code | Yes | Rohs Code | Yes |
Part Life Cycle Code | Obsolete | Part Package Code | TSOP2 |
Pin Count ! | 54 | Reach Compliance Code | compliant |
ECCN Code | EAR99 | HTS Code ! | 8542.32.00.02 |
Access Mode ! | FOUR BANK PAGE BURST | Access Time-Max | 5.4 ns |
Additional Feature ! | AUTO/SELF REFRESH | Clock Frequency-Max (fCLK) | 133 MHz |
I/O Type | COMMON | Interleaved Burst Length | 1,2,4,8 |
JESD-30 Code | R-PDSO-G54 | JESD-609 Code | e3 |
Length | 22.22 mm | Memory Density | 134217728 bit |
Memory IC Type | SYNCHRONOUS DRAM | Memory Width | 16 |
Number of Functions | 1 | Number of Ports ! | 1 |
Number of Terminals | 54 | Number of Words | 8388608 words |
Number of Words Code | 8000000 | Operating Mode ! | SYNCHRONOUS |
Operating Temperature-Max | 70 °C | Operating Temperature-Min | |
Organization | 8MX16 | Output Characteristics | 3-STATE |
Package Body Material | PLASTIC/EPOXY | Package Code | TSOP2 |
Package Equivalence Code | TSOP54,.46,32 | Package Shape | RECTANGULAR |
Package Style | SMALL OUTLINE, THIN PROFILE | Peak Reflow Temperature (Cel) | 260 |
Power Supplies ! | 3.3 V | Qualification Status ! | Not Qualified |
Refresh Cycles | 4096 | Seated Height-Max | 1.2 mm |
Self Refresh | YES | Sequential Burst Length | 1,2,4,8,FP |
Standby Current-Max | 0.002 A | Supply Current-Max | 0.31 mA |
Supply Voltage-Max (Vsup) | 3.6 V | Supply Voltage-Min (Vsup) | 3 V |
Supply Voltage-Nom (Vsup) | 3.3 V | Surface Mount ! | YES |
Technology | CMOS | Temperature Grade ! | COMMERCIAL |
Terminal Finish | Matte Tin (Sn) | Terminal Form ! | GULL WING |
Terminal Pitch ! | 0.8 mm | Terminal Position | DUAL |
Time@Peak Reflow Temperature-Max (s) | 30 | Width | 10.16 mm |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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