MT48LC16M16A2P-6AIT
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54MT48LC16M16A2P-6AIT
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
品質保證
品質保證
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認證
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運輸與付款
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服務與包裝
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自發貨之日起 90 天內發起申請。
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例子
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剪膠帶
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管或託盤
MT48LC16M16A2P-6AIT 數據表
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目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
General DescriptionThe 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.Features• PC100- and PC133-compliant• Fully synchronous; all signals registered on positive edge of system clock• Internal pipelined operation; column address can be changed every clock cycle• Internal banks for hiding row access/precharge• Programmable burst lengths: 1, 2, 4, 8, or full page• Auto precharge, includes concurrent auto precharge, and auto refresh modes• Self refresh mode• 64ms, 8,192-cycle refresh• LVTTL-compatible inputs and outputs• Single +3.3V ±0.3V power supply
主要特徵
- PC100- and PC133-compliant
- Fully synchronous; all signals registered on positive edge of system clock
- Internal, pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Programmable burst lengths: 1, 2, 4, 8, or full page
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- Self refresh mode (not available on AT devices)
- Auto refresh
- – 64ms, 8192-cycle refresh (commercial and industrial)
- – 16ms, 8192-cycle refresh (automotive)
- LVTTL-compatible inputs and outputs
- Single 3.3V ±0.3V power supply
![MICRON Inventory MICRON Inventory](/files/uploads/inventory/micron/micron.jpg)
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Pbfree Code | Yes | Rohs Code | Yes |
Part Life Cycle Code | Active | Part Package Code | TSOP2 |
Pin Count ! | 54 | Reach Compliance Code | compliant |
ECCN Code | EAR99 | HTS Code ! | 8542.32.00.24 |
Access Mode ! | FOUR BANK PAGE BURST | Access Time-Max | 5.4 ns |
Additional Feature ! | AUTO/SELF REFRESH | Clock Frequency-Max (fCLK) | 167 MHz |
I/O Type | COMMON | Interleaved Burst Length | 1,2,4,8 |
JESD-30 Code | R-PDSO-G54 | JESD-609 Code | e3 |
Length | 22.22 mm | Memory Density | 268435456 bit |
Memory IC Type | SYNCHRONOUS DRAM | Memory Width | 16 |
Moisture Sensitivity Level | 1 | Number of Functions | 1 |
Number of Ports ! | 1 | Number of Terminals | 54 |
Number of Words | 16777216 words | Number of Words Code | 16000000 |
Operating Mode ! | SYNCHRONOUS | Operating Temperature-Max | 85 °C |
Operating Temperature-Min | -40 °C | Organization | 16MX16 |
Output Characteristics | 3-STATE | Package Body Material | PLASTIC/EPOXY |
Package Code | TSOP2 | Package Equivalence Code | TSOP54,.46,32 |
Package Shape | RECTANGULAR | Package Style | SMALL OUTLINE, THIN PROFILE |
Peak Reflow Temperature (Cel) | 260 | Power Supplies ! | 3.3 V |
Qualification Status ! | Not Qualified | Refresh Cycles | 8192 |
Seated Height-Max | 1.2 mm | Self Refresh | YES |
Sequential Burst Length | 1,2,4,8,FP | Supply Voltage-Max (Vsup) | 3.6 V |
Supply Voltage-Min (Vsup) | 3 V | Supply Voltage-Nom (Vsup) | 3.3 V |
Surface Mount ! | YES | Technology | CMOS |
Temperature Grade ! | INDUSTRIAL | Terminal Finish | MATTE TIN |
Terminal Form ! | GULL WING | Terminal Pitch ! | 0.8 mm |
Terminal Position | DUAL | Time@Peak Reflow Temperature-Max (s) | 30 |
Width | 10.16 mm |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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