MPC8544E
Features PCI/PCIe, 1Gb Ethernet, USB, and SEC functionalitiesMPC8544E
Features PCI/PCIe, 1Gb Ethernet, USB, and SEC functionalities
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製造商零件號 # : MPC8544E
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包裝/封裝: BGA
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製造商: FREESCALE
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產品分類 : Microprocessors
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MPC8544E 數據表
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詳細說明
MPC8544E OverviewThis section provides a high-level overview of MPC8544E features. Figure 1 shows the major functional units within the device.Key FeaturesThe following list provides an overview of the device feature set:• High-performance, 32-bit core enhanced by resources for embedded cores defined by the Power ISA, and built on Power Architecture® technology: — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte–4-Gbyte page sizes. — Enhanced hardware and software debug support — Performance monitor facility that is similar to, but separate from, the device performance monitor
主要特徵
- The following list provides an overview of the device feature set:
- High-performance 32-bit Book E–enhanced core built on Power Architecture™ technology:
- — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data.
- — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
- — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs.
- — 36-bit real addressing
- — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions.
- — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte–4-Gbyte page sizes.
- — Enhanced hardware and software debug support
- — Performance monitor facility that is similar to, but separate from, the device performance monitor
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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