H5TQ1G83BFR-H9C

High-density DDR SDRAM module with 128 megabytes organized in an 18-bit configuration in a Fine-pitch Ball Grid Array package with 78 pins
3,725 有效庫存

H5TQ1G83BFR-H9C

有效庫存3,725

High-density DDR SDRAM module with 128 megabytes organized in an 18-bit configuration in a Fine-pitch Ball Grid Array package with 78 pins

  • 製造商零件號 # : H5TQ1G83BFR-H9C

  • 包裝/封裝: FBGA-78

  • 製造商: SKHYNIX

  • 產品分類 : Application Specific Clock/Timing

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H5TQ1G83BFR-H9C 數據表
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詳細說明

The H5TQ2G43CFR-xxC, H5TQ2G83CFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.FEATURES• VDD=VDDQ=1.5V +/- 0.075V• Fully differential clock inputs (CK, CK) operation• Differential Data Strobe (DQS, DQS)• On chip DLL align DQ, DQS and DQS transition with CK  transition• DM masks write data-in at the both rising and falling  edges of the data strobe• All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported• Programmable additive latency 0, CL-1, and CL-2  supported• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10• Programmable burst length 4/8 with both nibble  sequential and interleave mode• BL switch on the fly• 8banks• Average Refresh Cycle (Tcase of0 oC~ 95oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC• JEDEC standard 78ball FBGA(x4/x8)• Driver strength selected by EMRS• Dynamic On Die Termination supported• Asynchronous RESET pin supported• ZQ calibration supported• TDQS (Termination Data Strobe) supported (x8 only)• Write Levelization supported• 8 bit pre-fetch• This product in compliance with the RoHS directive.

主要特徵

  • VDD=VDDQ=1.5V +/- 0.075V
  • Fully differential clock inputs (CK, CK) operation
  • Differential Data Strobe (DQS, DQS)
  • On chip DLL align DQ, DQS and DQS transition with CK 
  • transition
  • DM masks write data-in at the both rising and falling 
  • edges of the data strobe
  • All addresses and control inputs except data, 
  • data strobes and data masks latched on the 
  • rising edges of the clock
  • Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13
  • and 14 supported
  • Programmable additive latency 0, CL-1, and CL-2 
  • supported
  • Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
  • Programmable burst length 4/8 with both nibble 
  • sequential and interleave mode
  • BL switch on the fly
  • 8banks
  • Average Refresh Cycle (Tcase of0 oC~ 95oC)
  • - 7.8 µs at 0oC ~ 85 oC
  • - 3.9 µs at 85oC ~ 95 oC
  • JEDEC standard 78ball FBGA(x4/x8)
  • Driver strength selected by EMRS
  • Dynamic On Die Termination supported
  • Asynchronous RESET pin supported
  • ZQ calibration supported
  • TDQS (Termination Data Strobe) supported (x8 only)
  • Write Levelization supported
  • 8 bit pre-fetch
  • This product in compliance with the RoHS directive.

規格

以下是所選零件的基本參數，涉及零件的特性及其所屬類別。

Rohs Code Yes Part Life Cycle Code Obsolete
Part Package Code BGA Pin Count ! 78
Reach Compliance Code ECCN Code EAR99
HTS Code ! 8542.32.00.36 Access Mode ! MULTI BANK PAGE BURST
Access Time-Max 20 ns Additional Feature ! AUTO/SELF REFRESH
Clock Frequency-Max (fCLK) 667 MHz I/O Type COMMON
Interleaved Burst Length 4,8 JESD-30 Code R-PBGA-B78
JESD-609 Code e1 Length 11 mm
Memory Density 2415919104 bit Memory IC Type DDR3 DRAM
Memory Width 18 Number of Functions 1
Number of Ports ! 1 Number of Terminals 78
Number of Words 134217728 words Number of Words Code 128000000
Operating Mode ! SYNCHRONOUS Operating Temperature-Max 85 °C
Operating Temperature-Min Organization 128MX18
Output Characteristics 3-STATE Package Body Material PLASTIC/EPOXY
Package Code TFBGA Package Equivalence Code BGA78,9X13,32
Package Shape RECTANGULAR Package Style GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Cel) 260 Power Supplies ! 1.5 V
Qualification Status ! Not Qualified Refresh Cycles 8192
Seated Height-Max 1.2 mm Self Refresh YES
Sequential Burst Length 4,8 Supply Current-Max 0.2 mA
Supply Voltage-Max (Vsup) 1.575 V Supply Voltage-Min (Vsup) 1.425 V
Supply Voltage-Nom (Vsup) 1.5 V Surface Mount ! YES
Technology CMOS Temperature Grade ! OTHER
Terminal Finish Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5) Terminal Form ! BALL
Terminal Pitch ! 0.8 mm Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) 20 Width 7.5 mm

Specification Comparison

H5TQ1G83TFR vs H5TQ1G83TFR-H9C vs H5TQ1G83BFR-H9C H5TQ1G83BFR vs H5TQ1G83TFR-H9C vs H5TQ1G83BFR-H9C

數據表 PDF

數據表記錄了器件的特性、絕對最大額定值、應用等，這對於作為器件特定應用的整體指南大有裨益。

初步規格 H5TQ1G83BFR-H9C PDF 下載

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