A3PE3000-PQ208I

Name: A3PE3000-PQ208I
Rating: 4.5 (10 reviews)

FPGA A3PE3000-PQ208I

3,039 有效庫存

A3PE3000-PQ208I

有效庫存3,039

FPGA A3PE3000-PQ208I

製造商零件號 # : A3PE3000-PQ208I
包裝/封裝: PQFP-20
製造商: MICROSEMI
產品分類 : FPGAs (Field Programmable Gate Array)

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運輸與付款

關於運送

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關於付款

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服務與包裝

About After Sales Service

All Parts Extended Quality Guarantee

自發貨之日起 90 天內發起申請。

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關於包裝

在包裝方面，我們的產品均精心包裝在防靜電袋中，以提供ESD防靜電保護。外包裝堅固耐用且閉合牢固。我們支持各種包裝方法，例如捲帶式、切帶式、管式或託盤式。

例子

捲帶式

剪膠帶

管或託盤

A3PE3000-PQ208I 數據表

目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!

快速報價

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詳細說明

Product A3PE3000-PQ208I is a field-programmable gate array (FPGA) that stands out for its exceptional features and specifications. With 3 million system gates and a PQ208 package with 208 pins, this FPGA is well-suited for medium to large-scale digital designs. One of its key strengths lies in its robust security features, including tamper-resistant packaging and secure embedded authentication, making it an excellent choice for applications requiring high levels of security, such as military and aerospace systems

主要特徵

High Capacity
600 k to 3 Million System Gates
108 to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
1 kbit of FlashROM with Synchronous Interfacing
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock® Designed to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC®3E Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, Each with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz
ARM® Processor Support in ProASIC3E FPGAs
M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug

規格

以下是所選零件的基本參數，涉及零件的特性及其所屬類別。

Rohs Code	No	Part Life Cycle Code	Obsolete
Reach Compliance Code		HTS Code !	8542.39.00.01
Clock Frequency-Max	350 MHz	JESD-30 Code	S-PQFP-G208
JESD-609 Code	e0	Length	28 mm
Moisture Sensitivity Level	3	Number of CLBs	75264
Number of Equivalent Gates	3000000	Number of Inputs	147
Number of Logic Cells !	75264	Number of Outputs	147
Number of Terminals	208	Operating Temperature-Max	85 °C
Operating Temperature-Min	-40 °C	Organization	75264 CLBS, 3000000 GATES
Package Body Material	PLASTIC/EPOXY	Package Code	FQFP
Package Equivalence Code	QFP208,1.2SQ,20	Package Shape	SQUARE
Package Style	FLATPACK, FINE PITCH	Peak Reflow Temperature (Cel)	225
Power Supplies !	1.5/3.3 V	Programmable Logic Type !	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status !	Not Qualified	Seated Height-Max	4.1 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.425 V
Supply Voltage-Nom	1.5 V	Surface Mount !	YES
Technology	CMOS	Temperature Grade !	INDUSTRIAL
Terminal Finish	TIN LEAD	Terminal Form !	GULL WING
Terminal Pitch !	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	20	Width	28 mm