W9412G6JH-5
DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66W9412G6JH-5
DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 INCH, ROHS COMPLIANT, TSOP2-66
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W9412G6JH-5 數據表
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目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
GENERAL DESCRIPTIONW9425G6DH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.11 µm process technology, W9425G6DH delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9425G6DH is sorted into four speed grades: -4, -5, -6 and -75. The -4 is compliant to the DDR500/CL3 specification. The -5 is compliant to the DDR400/CL3 specification. The -6 is compliant to the DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the DDR266/CL2 specification (the 75I grade which is guaranteed to support -40°C ~ 85°C).FEATURES• 2.5V ±0.2V Power Supply for DDR266/DDR333• 2.6V ±0.1V Power Supply for DDR400/DDR500• Up to 250 MHz Clock Frequency• Double Data Rate architecture; two data transfers per clock cycle• Differential clock inputs (CLK and CLK )• DQS is edge-aligned with data for Read; center-aligned with data for Write• CAS Latency: 2, 2.5 and 3• Burst Length: 2, 4 and 8• Auto Refresh and Self Refresh• Precharged Power Down and Active Power Down• Write Data Mask• Write Latency = 1• 7.8µS refresh interval (8K / 64 mS refresh)• Maximum burst refresh cycle: 8• Interface: SSTL_2• Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
主要特徵
- 2.5V ±0.2V Power Supply for DDR266/DDR333
- 2.6V ±0.1V Power Supply for DDR400/DDR500
- Up to 250 MHz Clock Frequency
- Double Data Rate architecture; two data transfers per clock cycle
- Differential clock inputs (CLK and CLK )
- DQS is edge-aligned with data for Read; center-aligned with data for Write
- CAS Latency: 2, 2.5 and 3
- Burst Length: 2, 4 and 8
- Auto Refresh and Self Refresh
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = 1
- 7.8µS refresh interval (8K / 64 mS refresh)
- Maximum burst refresh cycle: 8
- Interface: SSTL_2
- Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Rohs Code | Yes | Part Life Cycle Code | Obsolete |
Part Package Code | TSOP2 | Pin Count ! | 66 |
Reach Compliance Code | ECCN Code | EAR99 | |
HTS Code ! | 8542.32.00.02 | Access Mode ! | FOUR BANK PAGE BURST |
Access Time-Max | 0.7 ns | Additional Feature ! | AUTO/SELF REFRESH |
Clock Frequency-Max (fCLK) | 200 MHz | I/O Type | COMMON |
Interleaved Burst Length | 2,4,8 | JESD-30 Code | R-PDSO-G66 |
JESD-609 Code | e3 | Length | 22.22 mm |
Memory Density | 134217728 bit | Memory IC Type | DDR1 DRAM |
Memory Width | 16 | Number of Functions | 1 |
Number of Ports ! | 1 | Number of Terminals | 66 |
Number of Words | 8388608 words | Number of Words Code | 8000000 |
Operating Mode ! | SYNCHRONOUS | Operating Temperature-Max | 70 °C |
Operating Temperature-Min | Organization | 8MX16 | |
Output Characteristics | 3-STATE | Package Body Material | PLASTIC/EPOXY |
Package Code | TSOP2 | Package Equivalence Code | TSSOP66,.46 |
Package Shape | RECTANGULAR | Package Style | SMALL OUTLINE, THIN PROFILE |
Power Supplies ! | 2.5 V | Qualification Status ! | Not Qualified |
Refresh Cycles | 4096 | Seated Height-Max | 1.2 mm |
Self Refresh | YES | Sequential Burst Length | 2,4,8 |
Standby Current-Max | 0.005 A | Supply Current-Max | 0.15 mA |
Supply Voltage-Max (Vsup) | 2.7 V | Supply Voltage-Min (Vsup) | 2.3 V |
Supply Voltage-Nom (Vsup) | 2.5 V | Surface Mount ! | YES |
Technology | CMOS | Temperature Grade ! | COMMERCIAL |
Terminal Finish | TIN | Terminal Form ! | GULL WING |
Terminal Pitch ! | 0.65 mm | Terminal Position | DUAL |
Width | 10.16 mm |
Specification Comparison
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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