W90N745CDG
Component used in electronic systems
品質保證
品質保證
從我們的供應鍊網路採購的所有零件都經過嚴格的進貨檢驗流程。 這種細緻的檢查可確保客戶收到的零件是正品並符合要求的標準。 此外,我們還保存這些檢查的詳細記錄,以確保整個供應鏈的透明度和可追溯性。
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認證
我們已成功獲得各項認證標準,並建立了自己的專業檢測實驗室。 這確保了我們向客戶提供的每件產品都符合最高的品質標準。 我們遵守嚴格的測試協議,以保持我們產品的一致性和準確性。 為了確保我們的產品是原裝正品,我們還與信譽良好的第三方檢測機構合作進行嚴格的品質測試。 我們對品質的承諾延伸到滿足行業、法律、監管和 ISO 9001:2015 的要求。
運輸與付款
運輸與付款
關於運送
我們通常會在幾個工作日內通過可靠的運輸公司(例如 FedEx、SF、UPS 或 DHL)運送訂單。 我們還支持其他運輸方式。 如果您想詢問具體的運輸細節或費用,請隨時與我們聯繫。
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![pelican](/img//questionContentpelican.png)
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![chunghwa post](/img//questionContentchunghwapost.png)
關於付款
我們接受多種支付方式,包括VISA、MasterCard、銀聯、西聯、PayPal等渠道。
如果您有特定的付款方式或想詢問費率和其他詳細信息,請隨時與我們聯繫。
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電匯
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Paypal
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信用卡
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西聯匯款
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速匯金
服務與包裝
服務與包裝
About After Sales Service
All Parts Extended Quality Guarantee
自發貨之日起 90 天內發起申請。
與我們的工作人員確認退貨或換貨。
保持貨物收到時的原始狀態。
最後請注意,退貨或換貨的資格取決於對退貨商品實際狀況的評估。 在完成退貨或換貨流程之前,我們將評估收到的貨物。 如果您對退貨或換貨有任何疑問或需要進一步幫助,請隨時通過以下方式聯絡我們: [email protected]
關於包裝
在包裝方面,我們的產品均精心包裝在防靜電袋中,以提供ESD防靜電保護。 外包裝堅固耐用且閉合牢固。 我們支持各種包裝方法,例如捲帶式、切帶式、管式或託盤式。
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例子
![捲帶式](/img/Tape and Reel.png)
捲帶式
![剪膠帶](/img/Cut Tape.png)
剪膠帶
![管或託盤](/img/Tube or Tray.png)
管或託盤
W90N745CDG 數據表
![no-price](/img/no-price.jpg)
目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
General DescriptionThe W90210F Embedded Controller is part of Winbond¢s W90K Embedded processor family. The processor is a high-performance, highly integrated 32-bit processor intended for a wide range of embedded applications, such as set-top box, web browser, X-terminal, and visual/data communication devices..FeaturesMain features of the W90210F• PA-RISC architecture PA-RISC 1.1 third edition instruction set PA-RISC level zero implementation Support PA-RISC Multimedia Extension 1.0 instruction set W90K binary compatible for user software• High-performance implementation Five-stage pipeline Precise, efficient handling of pipeline stalls and exceptions Delayed branch with static branch prediction Forward: not taken Backward: taken One-cycle stall when prediction is wrong HIT under miss Both load and store can be queued when miss Load/store single cycle execution after previous miss• On-chip cache memory Internal I-cache: Direct mapped, 4 KB cache (256 entries, four words/entry) Wrap around fetching when cache miss Cache freeze capability Internal D-cache: 2-way set associative, 2 KB cache (2 ´64 entries, four words/entry) Write-back cache with write buffer Write-through option New line send to CPU before dirty line write back• Enhanced debug capability Debug SFU supports both instruction breakpoints and data breakpoints• High on-chip integration and simple I/O interface 486-like bus interface for CPU core Memory controller to support four banks of DRAM and ROM/FLASH ROM 2-channel 8-bit DMA controller PCI bridge Two Serial ports with FIFO Extended Capabilities Port (ECP) Two 24-bit timer/counters• Power Down mode Provide power down mode for power saving operation
主要特徵
- Main features of the W90210F
- PA-RISC architecture
- PA-RISC 1.1 third edition instruction set
- PA-RISC level zero implementation
- Support PA-RISC Multimedia Extension 1.0 instruction set
- W90K binary compatible for user software
- High-performance implementation
- Five-stage pipeline
- Precise, efficient handling of pipeline stalls and exceptions
- Delayed branch with static branch prediction
- Forward: not taken
- Backward: taken
- One-cycle stall when prediction is wrong
- HIT under miss
- Both load and store can be queued when miss
- Load/store single cycle execution after previous miss
- On-chip cache memory
- Internal I-cache: Direct mapped, 4 KB cache (256 entries, four words/entry)
- Wrap around fetching when cache miss
- Cache freeze capability
- Internal D-cache: 2-way set associative, 2 KB cache (2 ´64 entries, four words/entry)
- Write-back cache with write buffer
- Write-through option
- New line send to CPU before dirty line write back
- Enhanced debug capability
- Debug SFU supports both instruction breakpoints and data breakpoints
- High on-chip integration and simple I/O interface
- 486-like bus interface for CPU core
- Memory controller to support four banks of DRAM and ROM/FLASH ROM
- 2-channel 8-bit DMA controller
- PCI bridge
- Two Serial ports with FIFO
- Extended Capabilities Port (ECP)
- Two 24-bit timer/counters
- Power Down mode
- Provide power down mode for power saving operation
![NUVOTON Inventory NUVOTON Inventory](/files/uploads/inventory/nuvoton/nuvoton.jpg)
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Part Life Cycle Code | Active | Reach Compliance Code | compliant |
ECCN Code | 3A991.A.2 | HTS Code ! | 8542.31.00.01 |
Has ADC | YES | Address Bus Width ! | 21 |
Bit Size | 32 | Clock Frequency-Max | 30 MHz |
DAC Channels | NO | DMA Channels | YES |
External Data Bus Width | 16 | Length | 14 mm |
Number of I/O Lines | 31 | Number of Terminals | 128 |
PWM Channels | YES | Package Code | LFQFP |
Package Shape | SQUARE | Package Style | FLATPACK, LOW PROFILE, FINE PITCH |
Speed | 80 MHz | Supply Voltage-Max | 1.98 V |
Supply Voltage-Min | 1.62 V | Supply Voltage-Nom | 1.8 V |
Surface Mount ! | YES | Terminal Form ! | GULL WING |
Terminal Pitch ! | 0.4 mm | Terminal Position | QUAD |
Width | 14 mm |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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