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RTL8308B
Network Interface featuring CMOS Technology in a PQFP128 Package
RTL8308B
Network Interface featuring CMOS Technology in a PQFP128 Package
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RTL8308B 數據表
目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
General DescriptionThe RTL8308B is a 128-pin, low cost and ultra low power consumption 8-port 10/100M Ethernet switch controller. It is integrated both with a 2M bit embedded DRAM, as a packet buffer, and an 8K entry address table. The RTL8308B supports the reduced MII (RMII) interface. Only a single 50MHz oscillator is needed and the EEPROM is optional, which can save BOM costs. In addition, the RTL8308B provides an LED display to indicate a network loop existence.The RTL8308B provides eight 10/100 Mbps RMII Ethernet ports. Each port can operate in 10 Mbps or 100 Mbps data rate, and in full or half duplex mode. Speed, duplex, link status and flow control can be acquired by periodically polling the status of the PHY devices via MDIO.Features■ Supports eight 10/100Mbps Ethernet ports with RMII interface■ Provides forwarding of non-blocking and non-head-of-line-blocking■ 2M bit DRAM built in as a packet storage buffer■ Page based buffer management to efficiently utilize the internal packet buffer■ Ultra low power consumption with less than 160mA at 3.3V operating voltage■ Embedded 8K entry look-up table and 128 entry CAM■ Supports address hashing or direct mapping for look-up table■ 128-entry CAM is used to eliminate the hash collision issues■ Supports full and half duplex operation■ Link, speed and duplex status are auto-detected via MDIO■ Broadcast storm control■ Flow control fully supported: ● Half-duplex: back pressure ● Full-duplex: IEEE 802.3X■ Auto-negotiated Full-duplex flow control by writing the ability via MDIO to external PHY■ Supports Store-and-forward and cut-through operation■ Provides an LED display to indicate network loop existence■ Reversible PHYAD order for diverse PHY usage■ 3.3V 24LC02 interface■ Optional EEPROM 24LC02 for Loop detect configuration■ 128-pin PQFP, 0.35 um, 3.3V CMOS technology
主要特徵
- Supports eight 10/100Mbps Ethernet ports with RMII interface
- Provides forwarding of non-blocking and non-head-of-line-blocking
- 2M bit DRAM built in as a packet storage buffer
- Page based buffer management to efficiently utilize the internal packet buffer
- Ultra low power consumption with less than 160mA at 3.3V operating voltage
- Embedded 8K entry look-up table and 128 entry CAM
- Supports address hashing or direct mapping for look-up table
- 128-entry CAM is used to eliminate the hash collision issues
- Supports full and half duplex operation
- Link, speed and duplex status are auto-detected via MDIO
- Broadcast storm control
- Flow control fully supported:
- Half-duplex: back pressure
- Full-duplex: IEEE 802.3X
- Auto-negotiated Full-duplex flow control by writing the ability via MDIO to external PHY
- Supports Store-and-forward and cut-through operation
- Provides an LED display to indicate network loop existence
- Reversible PHYAD order for diverse PHY usage
- 3.3V 24LC02 interface
- Optional EEPROM 24LC02 for Loop detect configuration
- 128-pin PQFP, 0.35 um, 3.3V CMOS technology
規格
以下是所選零件的基本參數，涉及零件的特性及其所屬類別。
| Part Life Cycle Code | Obsolete | Reach Compliance Code | |
| HTS Code ! | 8542.39.00.01 | JESD-30 Code | R-PQFP-G128 |
| Number of Terminals | 128 | Operating Temperature-Max | 70 °C |
| Operating Temperature-Min | Package Body Material | PLASTIC/EPOXY | |
| Package Code | QFP | Package Equivalence Code | QFP128,.67X.93,20 |
| Package Shape | RECTANGULAR | Package Style | FLATPACK |
| Power Supplies ! | 3.3 V | Qualification Status ! | Not Qualified |
| Supply Current-Max | 160 mA | Supply Voltage-Nom | 3.3 V |
| Surface Mount ! | YES | Technology | CMOS |
| Temperature Grade ! | COMMERCIAL | Terminal Form ! | GULL WING |
| Terminal Pitch ! | 0.5 mm | Terminal Position | QUAD |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等，這對於作為器件特定應用的整體指南大有裨益。
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