PIC24FJ128GL306-I/MR

Name: PIC24FJ128GL306-I/MR
Rating: 4.5 (10 reviews)

Microcontroller solution for high-performance applications requiring large memory storage

7,767 有效庫存

PIC24FJ128GL306-I/MR

有效庫存7,767

Microcontroller solution for high-performance applications requiring large memory storage

製造商零件號 # : PIC24FJ128GL306-I/MR
包裝/封裝: QFN-64
製造商: Microchip
產品分類 : Microcontrollers

品質保證

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About After Sales Service

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關於包裝

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例子

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PIC24FJ128GL306-I/MR 數據表

目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!

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還要別的嗎？

詳細說明

Safety and security are at the forefront of the design of these MCUs. Hardware safety features and secure protection schemes ensure that your applications are protected from potential threats. Memory protection schemes like Flash ICSP™ Write Inhibit and CodeGuard™ Flash Security provide additional layers of security, while features like CryptoAuthentication™ chips enable you to implement robust security measures in your designs

主要特徵

Up to 256 segments (8x commons and 32x segments)
Core independent autonomous animation: Alternating dual display, blinking and blanking
LCD Charge Pump for contrast management in battery-powered applications
External bias option for reducing power consumption
Operation in power-saving modes

2.0V to 3.6V, -40°C to 125°C, up to 16 MIPS operation
Single-cycle instruction execution
16 x 16 Hardware Multiply, and 32-bit x 16-bit Hardware Divider
C compiler optimized instruction set system
AEC Q100 Grade 1 qualification

Ultra-low-power operation with sleep current down to nA with full RAM retention
A range of power-saving modes to reduce current consumption, while balancing performance: PMD bits, DOZE, Idle, Sleep and Retention Sleep modes
A range of Core Independent Peripherals (CIPs) that operate in power saving modes, while off-loading the Central Processing Unit (CPU)

Flash ‘One Time Programming’ (OTP) by ICSP™ Write Inhibit that offers an ability to disable Flash erase/write/debug operations
CodeGuard™ Flash protection to manage memory partitions and access restrictions
120-bit Unique Device ID, 256 bytes User OTP and the above protection schemes make an ideal combination of complementary features to implement security together with the CryptoAuthentication™ devices in a secure application

Flash with Error Correction Code (ECC) and Fault Injection for memory integrity check (Single error correction and Double error detection)
Dead-Man Timer (DMT) clocked by instruction fetches for monitoring the health of software
Windowed WatchDog Timer (WWDT) for system supervision
CodeGuard™ Flash protection for memory partition and access restriction
Fail-Safe Clock Monitor (FSCM) for clock fault management
Enhanced Programmable Cyclic Redundancy Check (CRC), Programmable High-Low Voltage Detect (HLVD), Brown-out Reset (BOR) and Power-on Reset (POR)
Class B Safety Library, IEC 60730

Up to 17-Channel, 400Ksps, 10/12-Bit Analog-to-Digital Converter (ADC)
Low-voltage boost for input
Bandgap reference input feature
Core Independent windowed threshold compare feature
Auto-scan feature
Operation in power-saving modes
Three Analog Comparators with input multiplexing and programmable reference voltage generators

5x 16-bit or 2x 32-bit dedicated timer/counters
14x PWM or Output Compare (OC) outputs with 5 independent timer bases – Multiple Capture Compare PWM (MCCP)
5x Input Captures (IC) – Multiple Capture Compare PWM (MCCP)
A total of 15x 16-bit or 7x 32-bit timer/counters
Hardware Real-Time Clock Calendar (RTCC) with Timestamping

4x Configurable Logic Cells (CLCs)
5x Multiple Capture Compare PWMs (MCCPs)
Segmented LCD controller with Core Independent Animation, up to 256 segments (8 commons x 32 segments)
ADC controller with threshold compare and automatic triggers
Direct Memory Access (DMA) with 6 channels, supporting UART, SPI, ADC, and more

4x UARTs supporting LIN/J2602 and IrDA®
2x SPI/I2S, up to 25 MHz operation
2x I2C Master and Slave w/Address Masking, PMBus™ and IPMI support

On-chip 8 MHz Fast RC (FRC), and 32 kHz Low-Power RC (LPRC) and Secondary (SOSC) oscillators
Programmable PLL with external oscillator clock sources and Reference Clock Output (REFO)
Fail-Safe Clock Monitor (FSCM)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) supporting two-speed start-up

MPLAB Code Configurator (MCC) support
Peripheral Pin Select (PPS) for flexible pin mapping
Configurable interrupt-on change on all IOs
In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2-pins
JTAG Boundary Scan Support

規格

以下是所選零件的基本參數，涉及零件的特性及其所屬類別。

CPU Type	16-bit PIC MCU	CPU Speed (MHz)	16
Program Memory Size (KB)	128	Multiple Flash Panels	No
Direct Memory Access (DMA) Channels	6	Temp. Range Min.(C°)	-40
Temp. Range Max.(C°)	125	Operation Voltage Min.(V)	2
Operation Voltage Max.(V)	3.6	Pin Count !	64
Low Power	Yes	Number of Comparators	3
Number of ADCs	1	ADC Channels	17
Max ADC Resolution (bits)	12	Max ADC Sampling Rate (ksps)	400
Number of DACs	0	DAC outputs	0
Max DAC Resolution (bits)	0	Hardware RTCC	Yes
Motor Control PWM Channels	0	SMPS PWM Channels	0
Number of PWM Time Bases	5	Output Compare Channels	5
USB Interface	None	Number of CAN Modules	0
Type of CAN module	None	Crypto Engine	No
Quadrature Encoder Interface (QEI)	0	Segment LCD	256
LCD/Graphics Interface	No	Configurable Logic Cell Modules (CLC /CCL)	4
Peripheral Pin Select (PPS)/Pin Muxing	Yes	Supported in MPLAB Code Configurator	Yes