PDTC115EU
TRANSISTOR 100 mA, 50 V, NPN, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, SC-70, 3 PIN, BIP General Purpose Small SignalPDTC115EU
TRANSISTOR 100 mA, 50 V, NPN, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, SC-70, 3 PIN, BIP General Purpose Small Signal
品質保證
品質保證
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認證
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運輸與付款
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服務與包裝
服務與包裝
About After Sales Service
All Parts Extended Quality Guarantee
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例子
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剪膠帶
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管或託盤
PDTC115EU 數據表
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目前的價格方案正在編制中。請聯絡我們的客戶服務團隊獲取最新的價格資訊。感謝您的理解和支援!
詳細說明
NPN resistor equipped transistorPDTC115EE SOT416 PDTC115EEF SOT490 PDTC115EK SOT346 PDTC115EM SOT883 PDTC115ES SOT54 (TO-92) PDTC115ET SOT23 PDTC115EU SOT323 • Built-in bias resistors • Simplified circuit design • Reduction of component count • Reduced pick and place costs.
主要特徵
- Built-in bias resistors
- Simplified circuit design
- Reduction of component count
- Reduced pick and place costs.
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Pbfree Code | Yes | Rohs Code | Yes |
Part Life Cycle Code | Transferred | Part Package Code | SC-70 |
Pin Count ! | 3 | Reach Compliance Code | compliant |
ECCN Code | EAR99 | Additional Feature ! | BUILT IN BIAS RESISTANCE RATIO IS 1 |
Collector Current-Max (IC) | 0.1 A | Collector-Emitter Voltage-Max | 50 V |
Configuration | SINGLE WITH BUILT-IN RESISTOR | DC Current Gain-Min (hFE) | 80 |
JESD-30 Code | R-PDSO-G3 | JESD-609 Code | e3 |
Moisture Sensitivity Level | 1 | Number of Elements | 1 |
Number of Terminals | 3 | Operating Temperature-Max | 150 °C |
Package Body Material | PLASTIC/EPOXY | Package Shape | RECTANGULAR |
Package Style | SMALL OUTLINE | Peak Reflow Temperature (Cel) | 260 |
Polarity/Channel Type | NPN | Power Dissipation-Max (Abs) | 0.2 W |
Qualification Status ! | Not Qualified | Surface Mount ! | YES |
Terminal Finish | Tin (Sn) | Terminal Form ! | GULL WING |
Terminal Position | DUAL | Time@Peak Reflow Temperature-Max (s) | 30 |
Transistor Application | SWITCHING | Transistor Element Material | SILICON |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
常見問題解答
What is PDTC115EU?
The PDTC115EU is a digital NPN transistor array designed by Nexperia. It consists of two NPN transistors in a single package, providing an efficient solution for digital logic circuits, amplifiers, and switching applications.
How Does PDTC115EU Work?
The PDTC115EU works by amplifying or switching digital signals using its two NPN transistors. Each transistor can be independently controlled, allowing for versatile circuit design options. The compact package and dual-transistor configuration make it suitable for space-constrained applications.
How Many Pins does PDTC115EU have and What are the Functions of the Pinout Configuration?
The PDTC115EU is housed in a SOT666 surface-mount package. The pinout configuration includes:
- Base 1, Emitter 1, Collector 1: Pins for the first NPN transistor.
- Base 2, Emitter 2, Collector 2: Pins for the second NPN transistor.
What are the Pros and Cons of PDTC115EU?
Pros:
- Compact Design: Ideal for applications where space is limited.
- Dual Transistor Array: Provides flexibility in circuit design and saves board space.
- High Voltage Capability: Capable of handling moderate voltage levels.
- Cost-Effective: Offers dual transistors in a single package, reducing overall component cost.
Cons:
- Limited Current Handling: May not be suitable for high-current applications.
- Surface-Mount Package: Requires surface-mount soldering techniques for PCB assembly.
- Less Common Package Type: SOT666 package may not be as widely compatible as other package types.
Are There Any Equivalents/Alternatives to PDTC115EU for Recommendation?
- An equivalent part to the PDTC115EU is the BCP56 from NXP Semiconductors.
- Alternative dual NPN transistor arrays include the BC847BMT from ON Semiconductor and the MMBT2222ALT1G from ON Semiconductor.
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