ML86V7666TBZ03A
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ML86V7666TBZ03A 數據表
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詳細說明
OVERVIEWThe ML86410 is an LSI that encodes YUV (YCbCr) format digital video signals into MPEG-4-ASP format ones in real time.The LSI achieves high picture quality by a unique high-speed high-quality motion search method and a unique coding rate control method. For video input, the LSI supports progressive video output from camera modules and interlaced video output from NTSC/PAL digital video decoders.FEATURESImage encoding:− Encoding format · MPEG-4 Simple [email protected] 3 · MPEG-4 Advanced Simple [email protected] 5− Supported image · Progressive QVGA, 30 fps · Progressive VGA, 30 fps · Interlaced NTSC, 29.97 fps · Interlaced PAL, 25 fps− Output frame (with a frame skipping function) · QVGA/ VGA : 30/15/1/0.5 fps · NTSC : 29.97/14.985/0.999/0.4995 fps · PAL : 25/12.5/1/0.5 fps− Coding type · IIII · IPPP···− Encoding mode · CBR (Up to 6 Mbps) · VBR− Supports interlaced images (NTSC/PAL)− Unique high-speed high-quality motion search method− Unique coding rate control method− 4MV motion estimation− Detectes abnormality such as: · Camera input abnormality · Stream data readout abnormality · Set bit rate exceeded− Can suspend/restart encodingVideo interface:− QVGA (320 × 240 pixels) / VGA (640 × 480 pixels) : YCbCr (8-bit (YCbCr) (4:2:2) ) + sync, 27 MHz YUV (8-bit (YUV)(4:2:2)) + sync, 27 MHz− NTSC (720 × 480 pixels) ) / PAL (720 × 576 pixels) : ITU-R BT.656, 27 MHzNote:Although signals are input in 4:2:2 format, they are converted to 4:2:0 format before encoding processing.− Can choose the order in which fields are loaded during interlacing (Top first/Bottom first)− Can choose between the positive polarity and the negative polarity of CLKCAM when loading YUVDATA,VSYNC, or HSYNC− Clipping can be specified as no clipping or clipping in the range of 16≤Y,U,V≤240− For the interface, a 3.3 V I/O interface is used.Host CPU interface:− General-purpose 8-/16-bit data bus (can be connected directly with Oki’s ARM microcontroller series)− Operable as an I/O device in DMA mode from the host CPUExternal SDRAM interface:− 32-bit data bus, 2 MWords × 32 bits, 81 MHz (equivalent to PC133)− Automatic initialization sequence− Column address: 8/9/10 bits selectableInput clock:− System clock : 27 MHz− Video interface : 27 MHzPower management:− No power management function is providedPower supply voltage:− Core section : 1.35 to 1.65 V− I/O section : 3.0 to 3.6 V− PLL section : 1.35 to 1.65 VOperating frequency:− Internal : 81 MHz− Video interface section : 27 MHzOperating temperature (ambient temperature):− -20 to +85°CPackage:− 144-pin plastic LQFP (LQFP144-P-2020-0.50-ZK)
主要特徵
- Image encoding:
- − Encoding format
- · MPEG-4 Simple
- [email protected]
- · MPEG-4 Advanced Simple
- [email protected]
- − Supported image
- · Progressive QVGA, 30 fps
- · Progressive VGA, 30 fps
- · Interlaced NTSC, 29.97 fps
- · Interlaced PAL, 25 fps
- − Output frame (with a frame skipping function)
- · QVGA/ VGA : 30/15/1/0.5 fps
- · NTSC : 29.97/14.985/0.999/0.4995 fps
- · PAL : 25/12.5/1/0.5 fps
- − Coding type
- · IIII
- · IPPP···
- − Encoding mode
- · CBR (Up to 6 Mbps)
- − Supports interlaced images (NTSC/PAL)
- − Unique high-speed high-quality motion search method
- − Unique coding rate control method
- − 4MV motion estimation
- − Detectes abnormality such as:
- · Camera input abnormality
- · Stream data readout abnormality
- · Set bit rate exceeded
- − Can suspend/restart encoding
- Video interface:
- − QVGA (320 × 240 pixels) / VGA (640 × 480 pixels) :
- YCbCr (8-bit (YCbCr) (4:2:2) ) + sync, 27 MHz
- YUV (8-bit (YUV)(4:2:2)) + sync, 27 MHz
- − NTSC (720 × 480 pixels) ) / PAL (720 × 576 pixels) : ITU-R BT.656, 27 MHz
- Although signals are input in 4:2:2 format, they are converted to
- 4:2:0 format before encoding processing.
- − Can choose the order in which fields are loaded during interlacing (Top first/Bottom first)
- − Can choose between the positive polarity and the negative polarity of CLKCAM when loading YUVDATA,
- VSYNC, or HSYNC
- − Clipping can be specified as no clipping or clipping in the range of 16≤Y,U,V≤240
- − For the interface, a 3.3 V I/O interface is used.
- Host CPU interface:
- − General-purpose 8-/16-bit data bus (can be connected directly
- with Oki’s ARM microcontroller series)
- − Operable as an I/O device in DMA mode from the host CPU
- External SDRAM interface:
- − 32-bit data bus, 2 MWords × 32 bits, 81 MHz (equivalent to PC133)
- − Automatic initialization sequence
- − Column address: 8/9/10 bits selectable
- Input clock:
- − System clock : 27 MHz
- − Video interface : 27 MHz
- Power management:
- − No power management function is provided
- Power supply voltage:
- − Core section : 1.35 to 1.65 V
- − I/O section : 3.0 to 3.6 V
- − PLL section : 1.35 to 1.65 V
- Operating frequency:
- − Internal : 81 MHz
- − Video interface section : 27 MHz
- Operating temperature (ambient temperature):
- − -20 to +85°C
- Package:
- − 144-pin plastic LQFP (LQFP144-P-2020-0.50-ZK)
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Manufacturer | Oki Semiconductor | Product Category ! | IC Chips |
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