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MBM29F040C-90PFTN
IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,32PIN,PLASTICMBM29F040C-90PFTN
IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,32PIN,PLASTIC
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MBM29F040C-90PFTN 數據表
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詳細說明
■ GENERAL DESCRIPTION The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCCsupply. A 12.0 V VPPis not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. ■ FEATURES • Single 5.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) • Minimum 100,000 write/erase cycles • High performance55 ns maximum access time • Sector erase architecture 8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase. • Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector • Embedded Program™ Algorithms Automatically writes and verifies data at specified address • DataPolling and Toggle Bit feature for detection of program or erase cycle completion • Low VCCwrite inhibit ≤3.2 V • Sector protection Hardware method disables any combination of sectors from write or erase operations • Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device
主要特徵
- Single 5.0 V read, program and erase Minimizes system level power requirements
- Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
- Compatible with JEDEC-standard byte-wide pinouts
- 32-pin PLCC (Package suffix: PD)
- 32-pin TSOP(I) (Package suffix: PF)
- 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
- Minimum 100,000 write/erase cycles
- High performance
- 55 ns maximum access time
- Sector erase architecture
- 8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase.
- Embedded Erase™ Algorithms
- Automatically pre-programs and erases the chip or any sector
- Embedded Program™ Algorithms
- Automatically writes and verifies data at specified address
- DataPolling and Toggle Bit feature for detection of program or erase cycle completion
- Low VCCwrite inhibit ≤3.2 V
- Sector protection
- Hardware method disables any combination of sectors from write or erase operations
- Erase Suspend/Resume
- Suspends the erase operation to allow a read data in another sector within the same device
規格
以下是所選零件的基本參數，涉及零件的特性及其所屬類別。
| Part Life Cycle Code | Active | Reach Compliance Code | compliant |
| Access Time-Max | 90 ns | Command User Interface | YES |
| Data Polling | YES | Endurance | 100000 Write/Erase Cycles |
| JESD-30 Code | R-PDSO-G32 | Memory Density | 4194304 bit |
| Memory IC Type | FLASH | Memory Width | 8 |
| Number of Sectors/Size | 8 | Number of Terminals | 32 |
| Number of Words | 524288 words | Number of Words Code | 512000 |
| Operating Temperature-Max | 85 °C | Operating Temperature-Min | -40 °C |
| Organization | 512KX8 | Package Body Material | PLASTIC/EPOXY |
| Package Code | TSSOP | Package Equivalence Code | TSSOP32,.8,20 |
| Package Shape | RECTANGULAR | Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
| Parallel/Serial | PARALLEL | Power Supplies ! | 5 V |
| Qualification Status ! | Not Qualified | Sector Size | 64K |
| Standby Current-Max | 0.000005 A | Supply Current-Max | 0.045 mA |
| Supply Voltage-Nom (Vsup) | 5 V | Surface Mount ! | YES |
| Technology | CMOS | Temperature Grade ! | INDUSTRIAL |
| Terminal Form ! | GULL WING | Terminal Pitch ! | 0.5 mm |
| Terminal Position | DUAL | Toggle Bit | YES |
| Type | NOR TYPE |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等，這對於作為器件特定應用的整體指南大有裨益。
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