LP365M
IC QUAD COMPARATOR, 6000 uV OFFSET-MAX, 1000 ns RESPONSE TIME, PDSO16, PLASTIC, SMT-16, ComparatorLP365M
IC QUAD COMPARATOR, 6000 uV OFFSET-MAX, 1000 ns RESPONSE TIME, PDSO16, PLASTIC, SMT-16, Comparator
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服務與包裝
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LP365M 數據表
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詳細說明
General DescriptionThe GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.Features■ Bidirectional interface between GTLP and LVTTL logic levels■ Designed with edge rate control circuitry to reduce output noise on the GTLP port■ Partitioned as two 18-Bit transceivers with individual latch timing and output control■ VREF pin provides external supply reference voltage for receiver threshold adjustibility■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature■ TTL compatible driver and control inputs■ Designed using Fairchild advanced BiCMOS technology■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs■ Power up/down and power off high impedance for live insertion■ Open drain on GTLP to support wired-or connection■ Flow through pinout optimizes PCB layout■ D-type flip-flop, latch and transparent data paths■ A Port source/sink −24mA/+24mA■ B Port sink +50mA■ For more information see AN-5026, Using BGA Packages
主要特徵
- Bidirectional interface between GTLP and LVTTL logic levels
- Designed with edge rate control circuitry to reduce output noise on the GTLP port
- Partitioned as two 18-Bit transceivers with individual latch timing and output control
- VREF pin provides external supply reference voltage for receiver threshold adjustibility
- Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
- TTL compatible driver and control inputs
- Designed using Fairchild advanced BiCMOS technology
- Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs
- Power up/down and power off high impedance for live insertion
- Open drain on GTLP to support wired-or connection
- Flow through pinout optimizes PCB layout
- D-type flip-flop, latch and transparent data paths
- A Port source/sink −24mA/+24mA
- B Port sink +50mA
- For more information see AN-5026, Using BGA Packages
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Rohs Code | No | Part Life Cycle Code | Obsolete |
Part Package Code | SOIC | Pin Count ! | 16 |
Reach Compliance Code | ECCN Code | EAR99 | |
HTS Code ! | 8542.39.00.01 | Amplifier Type | COMPARATOR |
Average Bias Current-Max (IIB) | 0.3 µA | Bias Current-Max (IIB) @25C | 0.3 µA |
Input Offset Voltage-Max | 6000 µV | JESD-30 Code | R-PDSO-G16 |
JESD-609 Code | e0 | Length | 9.9 mm |
Neg Supply Voltage Limit-Max | -18 V | Neg Supply Voltage-Nom (Vsup) | -15 V |
Number of Functions | 4 | Number of Terminals | 16 |
Operating Temperature-Max | 70 °C | Operating Temperature-Min | |
Output Type | OPEN-COLLECTOR | Package Body Material | PLASTIC/EPOXY |
Package Code | SOP | Package Equivalence Code | SOP16,.25 |
Package Shape | RECTANGULAR | Package Style | SMALL OUTLINE |
Power Supplies ! | 5/+-15 V | Qualification Status ! | Not Qualified |
Response Time-Nom | 1000 ns | Seated Height-Max | 1.75 mm |
Supply Current-Max | 3.5 mA | Supply Voltage Limit-Max | 18 V |
Supply Voltage-Nom (Vsup) | 15 V | Surface Mount ! | YES |
Technology | BIPOLAR | Temperature Grade ! | COMMERCIAL |
Terminal Finish | TIN LEAD | Terminal Form ! | GULL WING |
Terminal Pitch ! | 1.27 mm | Terminal Position | DUAL |
Width | 3.9 mm |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。