LC4032ZE-7TN48I
With a total of 32 I/O pins, this device offers versatile connectivity options for various electronic designsLC4032ZE-7TN48I
With a total of 32 I/O pins, this device offers versatile connectivity options for various electronic designs
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LC4032ZE-7TN48I 數據表
價格 (USD)
數量 | 單價 | 總價 |
---|---|---|
1 | $2.234 | $2.23 |
250 | $0.865 | $216.25 |
500 | $0.834 | $417.00 |
1000 | $0.820 | $820.00 |
這些價格會受到市場波動的影響,需要提交報價才能取得最新價格。
詳細說明
Features■ High Performance • fMAX = 260MHz maximum operating frequency • tPD = 4.4ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output■ Ease of Design • Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls • Up to four global OE controls • Individual local OE control per I/O pin • Excellent First-Time-FitTM and refit • Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders■ Ultra Low Power • Standby current as low as 10µA typical • 1.8V core; low dynamic power • Operational down to 1.6V VCC • Superior solution for power sensitive consumer applications • Per pin pull-up, pull-down or bus keeper control* • Power Guard with multiple enable signals*■ Broad Device Offering • 32 to 256 macrocells • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) • Space-saving packages■ Easy System Integration • Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces • Hot-socketing support • Open-drain output option • Programmable output slew rate • 3.3V PCI compatible • I/O pins with fast setup path • Input hysteresis* • 1.8V core power supply • IEEE 1149.1 boundary scan testable • IEEE 1532 ISC compliant • 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP) • Pb-free package options (only) • On-chip user oscillator and timer*
主要特徵
- High Performance
- fMAX = 260MHz maximum operating frequency
- tPD = 4.4ns propagation delay
- Up to four global clock pins with programmable clock polarity control
- Up to 80 PTs per output
- Ease of Design
- Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
- Up to four global OE controls
- Individual local OE control per I/O pin
- Excellent First-Time-FitTM and refit
- Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
- Ultra Low Power
- Standby current as low as 10µA typical
- 1.8V core; low dynamic power
- Operational down to 1.6V VCC
- Superior solution for power sensitive consumer applications
- Per pin pull-up, pull-down or bus keeper control
- Power Guard with multiple enable signals
- Broad Device Offering
- 32 to 256 macrocells
- Multiple temperature range support
- – Commercial: 0 to 90°C junction (Tj)
- – Industrial: -40 to 105°C junction (Tj)
- Space-saving packages
- Easy System Integration
- Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O
- 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
- Hot-socketing support
- Open-drain output option
- Programmable output slew rate
- 3.3V PCI compatible
- I/O pins with fast setup path
- Input hysteresis
- 1.8V core power supply
- IEEE 1149.1 boundary scan testable
- IEEE 1532 ISC compliant
- 1.8V In-System Programmable (ISP™) using Boundary Scan Test Access Port (TAP)
- Pb-free package options (only)
- On-chip user oscillator and timer
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Rohs Code | Yes | Part Life Cycle Code | Active |
Part Package Code | QFP | Pin Count ! | 48 |
Reach Compliance Code | compliant | ECCN Code | EAR99 |
HTS Code ! | 8542.39.00.01 | Additional Feature ! | YES |
Clock Frequency-Max | 111 MHz | In-System Programmable | YES |
JESD-30 Code | S-PQFP-G48 | JESD-609 Code | e3 |
JTAG BST | YES | Length | 7 mm |
Moisture Sensitivity Level | 3 | Number of Dedicated Inputs | 4 |
Number of I/O Lines | 32 | Number of Macro Cells | 32 |
Number of Terminals | 48 | Organization | 4 DEDICATED INPUTS, 32 I/O |
Output Function ! | MACROCELL | Package Body Material | PLASTIC/EPOXY |
Package Code | TFQFP | Package Equivalence Code | TQFP48,.35SQ |
Package Shape | SQUARE | Package Style | FLATPACK, THIN PROFILE, FINE PITCH |
Peak Reflow Temperature (Cel) | 260 | Power Supplies ! | 1.8 V |
Programmable Logic Type ! | EE PLD | Propagation Delay ! | 7.5 ns |
Qualification Status ! | Not Qualified | Seated Height-Max | 1.2 mm |
Supply Voltage-Max | 1.9 V | Supply Voltage-Min | 1.7 V |
Supply Voltage-Nom | 1.8 V | Surface Mount ! | YES |
Technology | CMOS | Terminal Finish | MATTE TIN |
Terminal Form ! | GULL WING | Terminal Pitch ! | 0.5 mm |
Terminal Position | QUAD | Time@Peak Reflow Temperature-Max (s) | 40 |
Width | 7 mm |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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