CY37032P44-125AXC
Packaged in a 44-pin TQFP tray, this CPLD offers a compact and reliable solution for integrating custom logic functions into electronic systemsCY37032P44-125AXC
Packaged in a 44-pin TQFP tray, this CPLD offers a compact and reliable solution for integrating custom logic functions into electronic systems
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CY37032P44-125AXC 數據表
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詳細說明
General DescriptionThe Ultra37000™ family of CMOSCPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM).Features• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes• High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins• Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms — No delay for steering or sharing product terms• 3.3V and 5V versions• PCI-compatible[1]• Programmable bus-hold capabilities on all I/Os• Intelligent product term allocator provides: — 0 to 16 product terms to any macrocell — Product term steering onan individual basis — Product term sharing among local macrocells• Flexible clocking — Four synchronous clocks per device — Product term clocking — Clock polarity control per logic block• Consistent package/pinout offering across all densities — Simplifies design migration — Same pinout for 3.3V and 5.0V devices• Packages — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages — Lead(Pb)-free packages available
主要特徵
- In-System Reprogrammable™ (ISR™) CMOS CPLDs
- — JTAG interface for reconfigurability
- — Design changes do not cause pinout changes
- — Design changes do not cause timing changes
- High density
- — 32 to 512 macrocells
- — 32 to 264 I/O pins
- — Five dedicated inputs including four clock pins
- Simple timing model
- — No fanout delays
- — No expander delays
- — No dedicated vs. I/O pin delays
- — No additional delay through PIM
- — No penalty for using full 16 product terms
- — No delay for steering or sharing product terms
- 3.3V and 5V versions
- PCI-compatible[1]
- Programmable bus-hold capabilities on all I/Os
- Intelligent product term allocator provides:
- — 0 to 16 product terms to any macrocell
- — Product term steering onan individual basis
- — Product term sharing among local macrocells
- Flexible clocking
- — Four synchronous clocks per device
- — Product term clocking
- — Clock polarity control per logic block
- Consistent package/pinout offering across all densities
- — Simplifies design migration
- — Same pinout for 3.3V and 5.0V devices
- Packages
- — 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages
- — Lead(Pb)-free packages available
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Category | Integrated Circuits (ICs)EmbeddedCPLDs (Complex Programmable Logic Devices) | Mfr | Infineon Technologies |
Series | Ultra37000™ | Package | Tape & Reel (TR) |
Product Status | Obsolete | Programmable | Verified |
Programmable Type ! | In-System Reprogrammable™ (ISR™) CMOS | Delay Time tpd(1) Max | 10 ns |
Voltage Supply - Internal | 4.75V ~ 5.25V | Number of Macrocells | 32 |
Number of I/O | 37 | Operating Temperature ! | 0°C ~ 70°C (TA) |
Mounting Type | Surface Mount | Package / Case | 44-LQFP |
Supplier Device Package | 44-TQFP (10x10) | Base Product Number | CY37032 |
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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