AT91SAM9263-CU
RISC Microcontroller
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AT91SAM9263-CU 數據表
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詳細說明
The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance.Features• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level Implementation Embedded Trace Macrocell™• Bus Matrix – Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth – Boot Mode Select Option, Remap Command• Embedded Memories – One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed – One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed – One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed• Dual External Bus Interface (EBI0 and EBI1) – EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® – EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash• DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control• Twenty Peripheral DMA Controller Channels (PDC)• LCD Controller – Supports Passive or Active Displays – Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers• Two D Graphics Accelerator – Line Draw, Block Transfer, Clipping, Commands Queuing• Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format• USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels• USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM• Ethernet MAC 10/100 Base-T – Media Independent Interface or Reduced Media Independent Interface – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit• Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Double Real-time Timer(Continue ...)
主要特徵
- Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
- – DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration
- – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
- – 220 MIPS at 200 MHz
- – Memory Management Unit
- – EmbeddedICE™, Debug Communication Channel Support
- – Mid-level Implementation Embedded Trace Macrocell™
- Bus Matrix
- – Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
- – Boot Mode Select Option, Remap Command
- Embedded Memories
- – One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
- – One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus
- Matrix Speed
- – One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
- Dual External Bus Interface (EBI0 and EBI1)
- – EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
- CompactFlash®
- – EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
- DMA Controller (DMAC)
- – Acts as one Bus Matrix Master
- – Embeds 2 Unidirectional Channels with Programmable Priority, Address
- Generation, Channel Buffering and Control
- Twenty Peripheral DMA Controller Channels (PDC)
- LCD Controller
- – Supports Passive or Active Displays
- – Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
- – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual
- Screen Buffers
- Two D Graphics Accelerator
- – Line Draw, Block Transfer, Clipping, Commands Queuing
- Image Sensor Interface
- – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
- – 12-bit Data Interface for Support of High Sensibility Sensors
- – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
- USB 2.0 Full Speed (12 Mbits per second) Host Double Port
- – Dual On-chip Transceivers
- – Integrated FIFOs and Dedicated DMA Channels
- USB 2.0 Full Speed (12 Mbits per second) Device Port
- – On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
- Ethernet MAC 10/100 Base-T
- – Media Independent Interface or Reduced Media Independent Interface
- – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
- Fully-featured System Controller, including
- – Reset Controller, Shutdown Controller
- – Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
- – Clock Generator and Power Management Controller
- – Advanced Interrupt Controller and Debug Unit
- – Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
- (Continue ...)
規格
以下是所選零件的基本參數,涉及零件的特性及其所屬類別。
Rohs Code | Yes | Part Life Cycle Code | Obsolete |
Part Package Code | BGA | Pin Count ! | 324 |
Reach Compliance Code | ECCN Code | 3A991.A.2 | |
HTS Code ! | 8542.31.00.01 | Has ADC | NO |
Additional Feature ! | ALSO REQUIRES 3.3V SUPPLY | Address Bus Width ! | 26 |
Bit Size | 32 | CPU Family | ARM9 |
Clock Frequency-Max | 50 MHz | DAC Channels | NO |
DMA Channels | YES | External Data Bus Width | 32 |
JESD-30 Code | S-PBGA-B324 | Length | 15 mm |
Number of I/O Lines | 160 | Number of Terminals | 324 |
Operating Temperature-Max | 85 °C | Operating Temperature-Min | -40 °C |
PWM Channels | YES | Package Body Material | PLASTIC/EPOXY |
Package Code | TFBGA | Package Equivalence Code | BGA324,18X18,32 |
Package Shape | SQUARE | Package Style | GRID ARRAY, THIN PROFILE, FINE PITCH |
Power Supplies ! | 1.2,1.8,3.3 V | Qualification Status ! | Not Qualified |
RAM (bytes) | 98304 | ROM (words) | 131072 |
ROM Programmability | FLASH | Seated Height-Max | 1.2 mm |
Speed | 240 MHz | Supply Voltage-Max | 1.32 V |
Supply Voltage-Min | 1.08 V | Supply Voltage-Nom | 1.2 V |
Surface Mount ! | YES | Technology | CMOS |
Temperature Grade ! | INDUSTRIAL | Terminal Form ! | BALL |
Terminal Pitch ! | 0.8 mm | Terminal Position | BOTTOM |
Width | 15 mm | uPs/uCs/Peripheral ICs Type | MICROCONTROLLER, RISC |
Product Category ! | Microprocessors - MPU | RoHS | Details |
Mounting Style | SMD/SMT | Package / Case | TFBGA-324 |
Series | 91S | Core | ARM926EJ-S |
Number of Cores | 1 Core | Data Bus Width | 32 bit |
Maximum Clock Frequency | 200 MHz | L1 Cache Instruction Memory | 16 kB |
L1 Cache Data Memory | 16 kB | Operating Supply Voltage ! | 1.2 V |
Minimum Operating Temperature | - 40 C | Maximum Operating Temperature ! | + 85 C |
Brand | Microchip Technology | Data RAM Size | 96 kB |
Data ROM Size | 128 kB | I/O Voltage | 1.8 V, 2.5 V, 3.3 V |
Interface Type | 2-Wire, CAN, SPI, UART, USB | Memory Type ! | L1 Cache, ROM, SRAM |
Moisture Sensitive | Yes | Number of I/Os | 160 I/O |
Number of Timers/Counters | 1 Timer | Processor Series | AT91SAM |
Product Type ! | Microprocessors - MPU | Factory Pack Quantity | 126 |
Subcategory | Microprocessors - MPU | Watchdog Timers | Watchdog Timer |
Specification Comparison
數據表 PDF
數據表記錄了器件的特性、絕對最大額定值、應用等,這對於作為器件特定應用的整體指南大有裨益。
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