AM3354BZCE60

Name: AM3354BZCE60
Rating: 4.5 (10 reviews)

ARM Cortex-A8 MPU

9,063 有效庫存

AM3354BZCE60

有效庫存9,063

ARM Cortex-A8 MPU

製造商零件號 # : AM3354BZCE60
包裝/封裝: NFBGA-298
零件狀態 : ACTIVE
製造商: Texas Instruments
產品分類 : Microprocessors
RoHS:

品質保證

從我們的供應鍊網路採購的所有零件都經過嚴格的進貨檢驗流程。這種細緻的檢查可確保客戶收到的零件是正品並符合要求的標準。此外，我們還保存這些檢查的詳細記錄，以確保整個供應鏈的透明度和可追溯性。

認證

我們已成功獲得各項認證標準，並建立了自己的專業檢測實驗室。這確保了我們向客戶提供的每件產品都符合最高的品質標準。我們遵守嚴格的測試協議，以保持我們產品的一致性和準確性。為了確保我們的產品是原裝正品，我們還與信譽良好的第三方檢測機構合作進行嚴格的品質測試。我們對品質的承諾延伸到滿足行業、法律、監管和 ISO 9001:2015 的要求。

運輸與付款

關於運送

我們通常會在幾個工作日內通過可靠的運輸公司（例如 FedEx、SF、UPS 或 DHL）運送訂單。我們還支持其他運輸方式。如果您想詢問具體的運輸細節或費用，請隨時與我們聯繫。

關於付款

我們接受多種支付方式，包括VISA、MasterCard、銀聯、西聯、PayPal等渠道。

如果您有特定的付款方式或想詢問費率和其他詳細信息，請隨時與我們聯繫。

電匯

Paypal

信用卡

西聯匯款

速匯金

服務與包裝

About After Sales Service

All Parts Extended Quality Guarantee

自發貨之日起 90 天內發起申請。

與我們的工作人員確認退貨或換貨。

保持貨物收到時的原始狀態。

最後請注意，退貨或換貨的資格取決於對退貨商品實際狀況的評估。在完成退貨或換貨流程之前，我們將評估收到的貨物。如果您對退貨或換貨有任何疑問或需要進一步幫助，請隨時通過以下方式聯絡我們： [email protected]

關於包裝

在包裝方面，我們的產品均精心包裝在防靜電袋中，以提供ESD防靜電保護。外包裝堅固耐用且閉合牢固。我們支持各種包裝方法，例如捲帶式、切帶式、管式或託盤式。

例子

捲帶式

剪膠帶

管或託盤

AM3354BZCE60 數據表

價格 (USD)

數量	單價	總價
1	$10.802	$10.80
200	$4.180	$836.00
500	$4.034	$2,017.00
1000	$3.961	$3,961.00

這些價格會受到市場波動的影響，需要提交報價才能取得最新價格。

快速報價

請提交詢價 AM3354BZCE60 或發送電子郵件給我們： Email: [email protected], 我們將在 12 小時內與您聯繫。

數量^*

聯絡人^*

郵箱^*

公司名稱

還要別的嗎？

詳細說明

With its advanced features and robust subsystems, the AM3354BZCE60 stands out as a top-tier microprocessor solution for a wide range of applications. The ARM Cortex-A8 processor at the core of the MPU subsystem ensures powerful processing capabilities, while the PRU-ICSS subsystem enables independent operation and real-time protocol support. The inclusion of the PowerVR SGX™ Graphics Accelerator subsystem further enhances the device's graphics processing capabilities, making it suitable for demanding applications such as display and gaming

主要特徵

Up to 1-GHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- SGX530 3D Graphics Engine
  - Tile-Based Architecture Delivering up to 20 Million Polygons per Second
  - Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
  - Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
  - Programmable High-Quality Image Anti-Aliasing
  - Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
- LCD Controller
  - Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
  - Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
  - Integrated LCD Interface Display Driver (LIDD) Controller
  - Integrated Raster Controller
  - Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
  - 512-Word Deep Internal FIFO
  - Supported Display Types:
    - Character Displays - Uses LIDD Controller to Program these Displays
    - Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
    - Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
  - Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
- Up to Three 32-Bit eCAP Modules
  - Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
- Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Security
- Crypto Hardware Accelerators (AES, SHA, RNG)
- Secure Boot (optional; requires custom part engagement with TI)
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Packages:
- 298-Pin S-PBGA-N298 Via Channel Package
  (ZCE Suffix), 0.65-mm Ball Pitch
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

規格

以下是所選零件的基本參數，涉及零件的特性及其所屬類別。

Arm CPU	1 Arm Cortex-A8	Arm (max) (MHz)	300, 600, 800, 1000
Coprocessors	GPU	CPU	32-bit
Graphics acceleration	1 3D	Display type	1 LCD
Protocols	Ethernet	Ethernet MAC	2-Port 10/100 PRU EMAC, 2-Port 1Gb switch
Hardware accelerators	SGX530 Graphics, Security Accelerator	Features	General purpose
Operating system	Linux, RTOS	Security	Cryptography, Device identity
Rating	Catalog	Power supply solution	TPS65216, TPS65218D0
Operating temperature range (°C)	-40 to 105, -40 to 90, 0 to 90

快速詢價

AM3354BZCE60

AM3354BZCE60

品質保證

運輸與付款

服務與包裝

價格 (USD)

快速報價

詳細說明

主要特徵

規格

關注我们

AM3354BZCE60

AM3354BZCE60

品質保證

運輸與付款

服務與包裝

價格 (USD)

快速報價

詳細說明

主要特徵

規格

推薦零件